PMID- 12964210
OWN - NLM
STAT- MEDLINE
DCOM- 20040108
LR  - 20191210
IS  - 0129-0657 (Print)
IS  - 0129-0657 (Linking)
VI  - 13
IP  - 4
DP  - 2003 Aug
TI  - FPGA implementation of a pyramidal Weightless Neural Networks learning system.
PG  - 225-37
AB  - A hardware architecture of a Probabilistic Logic Neuron (PLN) is presented. The 
      suggested model facilitates the on-chip learning of pyramidal Weightless Neural 
      Networks using a modified probabilistic search reward/penalty training algorithm. 
      The penalization strategy of the training algorithm depends on a predefined 
      parameter called the probabilistic search interval. A complete Weightless Neural 
      Network (WNN) learning system is modeled and implemented on Xilinx XC4005E Field 
      Programmable Gate Array (FPGA), allowing its architecture to be configurable. 
      Various experiments have been conducted to examine the feasibility and 
      performance of the WNN learning system. Results show that the system has a fast 
      convergence rate and good generalization ability.
FAU - Al-Alawi, Raida
AU  - Al-Alawi R
AD  - Department of Electrical and Electronic Engineering, University of Bahrain, PO 
      Box 32038, Bahrain. raida@ieee.org
LA  - eng
PT  - Journal Article
PL  - Singapore
TA  - Int J Neural Syst
JT  - International journal of neural systems
JID - 9100527
SB  - IM
MH  - Algorithms
MH  - *Computers
MH  - Models, Neurological
MH  - *Neural Networks, Computer
MH  - Neurons/physiology
EDAT- 2003/09/10 05:00
MHDA- 2004/01/09 05:00
CRDT- 2003/09/10 05:00
PHST- 2003/02/08 00:00 [received]
PHST- 2003/05/27 00:00 [accepted]
PHST- 2003/05/14 00:00 [revised]
PHST- 2003/09/10 05:00 [pubmed]
PHST- 2004/01/09 05:00 [medline]
PHST- 2003/09/10 05:00 [entrez]
AID - S012906570300156X [pii]
AID - 10.1142/S012906570300156X [doi]
PST - ppublish
SO  - Int J Neural Syst. 2003 Aug;13(4):225-37. doi: 10.1142/S012906570300156X.