PMID- 20385005
OWN - NLM
STAT- MEDLINE
DCOM- 20101027
LR  - 20211020
IS  - 1471-2105 (Electronic)
IS  - 1471-2105 (Linking)
VI  - 11
DP  - 2010 Apr 12
TI  - FPGA Acceleration of the phylogenetic likelihood function for Bayesian MCMC 
      inference methods.
PG  - 184
LID - 10.1186/1471-2105-11-184 [doi]
AB  - BACKGROUND: Likelihood (ML)-based phylogenetic inference has become a popular 
      method for estimating the evolutionary relationships among species based on 
      genomic sequence data. This method is used in applications such as RAxML, GARLI, 
      MrBayes, PAML, and PAUP. The Phylogenetic Likelihood Function (PLF) is an 
      important kernel computation for this method. The PLF consists of a loop with no 
      conditional behavior or dependencies between iterations. As such it contains a 
      high potential for exploiting parallelism using micro-architectural techniques. 
      In this paper, we describe a technique for mapping the PLF and supporting logic 
      onto a Field Programmable Gate Array (FPGA)-based co-processor. By leveraging the 
      FPGA's on-chip DSP modules and the high-bandwidth local memory attached to the 
      FPGA, the resultant co-processor can accelerate ML-based methods and outperform 
      state-of-the-art multi-core processors. RESULTS: We use the MrBayes 3 tool as a 
      framework for designing our co-processor. For large datasets, we estimate that 
      our accelerated MrBayes, if run on a current-generation FPGA, achieves a 10x 
      speedup relative to software running on a state-of-the-art server-class 
      microprocessor. The FPGA-based implementation achieves its performance by deeply 
      pipelining the likelihood computations, performing multiple floating-point 
      operations in parallel, and through a natural log approximation that is chosen 
      specifically to leverage a deeply pipelined custom architecture. CONCLUSIONS: 
      Heterogeneous computing, which combines general-purpose processors with 
      special-purpose co-processors such as FPGAs and GPUs, is a promising approach for 
      high-performance phylogeny inference as shown by the growing body of literature 
      in this field. FPGAs in particular are well-suited for this task because of their 
      low power consumption as compared to many-core processors and Graphics Processor 
      Units (GPUs).
FAU - Zierke, Stephanie
AU  - Zierke S
AD  - Department of Computer Science and Engineering, University of South Carolina, 
      Columbia, SC, USA.
FAU - Bakos, Jason D
AU  - Bakos JD
LA  - eng
PT  - Journal Article
PT  - Research Support, Non-U.S. Gov't
DEP - 20100412
PL  - England
TA  - BMC Bioinformatics
JT  - BMC bioinformatics
JID - 100965194
SB  - IM
MH  - Bayes Theorem
MH  - Likelihood Functions
MH  - *Phylogeny
MH  - Software
PMC - PMC2868009
EDAT- 2010/04/14 06:00
MHDA- 2010/10/28 06:00
PMCR- 2010/04/12
CRDT- 2010/04/14 06:00
PHST- 2009/05/18 00:00 [received]
PHST- 2010/04/12 00:00 [accepted]
PHST- 2010/04/14 06:00 [entrez]
PHST- 2010/04/14 06:00 [pubmed]
PHST- 2010/10/28 06:00 [medline]
PHST- 2010/04/12 00:00 [pmc-release]
AID - 1471-2105-11-184 [pii]
AID - 10.1186/1471-2105-11-184 [doi]
PST - epublish
SO  - BMC Bioinformatics. 2010 Apr 12;11:184. doi: 10.1186/1471-2105-11-184.