PMID- 28374681
OWN - NLM
STAT- PubMed-not-MEDLINE
DCOM- 20180723
LR  - 20180723
IS  - 1361-6528 (Electronic)
IS  - 0957-4484 (Linking)
VI  - 28
IP  - 17
DP  - 2017 Apr 28
TI  - A reliable and controllable graphene doping method compatible with current CMOS 
      technology and the demonstration of its device applications.
PG  - 175710
LID - 10.1088/1361-6528/aa6537 [doi]
AB  - The modulation of charge carrier concentration allows us to tune the Fermi level 
      (E (F)) of graphene thanks to the low electronic density of states near the E 
      (F). The introduced metal oxide thin films as well as the modified transfer 
      process can elaborately maneuver the amounts of charge carrier concentration in 
      graphene. The self-encapsulation provides a solution to overcome the stability 
      issues of metal oxide hole dopants. We have manipulated systematic graphene p-n 
      junction structures for electronic or photonic application-compatible doping 
      methods with current semiconducting process technology. We have demonstrated the 
      anticipated transport properties on the designed heterojunction devices with 
      non-destructive doping methods. This mitigates the device architecture limitation 
      imposed in previously known doping methods. Furthermore, we employed E 
      (F)-modulated graphene source/drain (S/D) electrodes in a low dimensional 
      transition metal dichalcogenide field effect transistor (TMDFET). We have 
      succeeded in fulfilling n-type, ambipolar, or p-type field effect transistors 
      (FETs) by moving around only the graphene work function. Besides, the 
      graphene/transition metal dichalcogenide (TMD) junction in either both p- and 
      n-type transistor reveals linear voltage dependence with the enhanced contact 
      resistance. We accomplished the complete conversion of p-/n-channel transistors 
      with S/D tunable electrodes. The E (F) modulation using metal oxide facilitates 
      graphene to access state-of-the-art complimentary-metal-oxide-semiconductor 
      (CMOS) technology.
FAU - Kim, Seonyeong
AU  - Kim S
AD  - Department of Physics, Sejong University, Seoul, 143-747, Republic of Korea.
FAU - Shin, Somyeong
AU  - Shin S
FAU - Kim, Taekwang
AU  - Kim T
FAU - Du, Hyewon
AU  - Du H
FAU - Song, Minho
AU  - Song M
FAU - Kim, Ki Soo
AU  - Kim KS
FAU - Cho, Seungmin
AU  - Cho S
FAU - Lee, Sang Wook
AU  - Lee SW
FAU - Seo, Sunae
AU  - Seo S
LA  - eng
PT  - Journal Article
PL  - England
TA  - Nanotechnology
JT  - Nanotechnology
JID - 101241272
EDAT- 2017/04/05 06:00
MHDA- 2017/04/05 06:01
CRDT- 2017/04/05 06:00
PHST- 2017/04/05 06:00 [entrez]
PHST- 2017/04/05 06:00 [pubmed]
PHST- 2017/04/05 06:01 [medline]
AID - 10.1088/1361-6528/aa6537 [doi]
PST - ppublish
SO  - Nanotechnology. 2017 Apr 28;28(17):175710. doi: 10.1088/1361-6528/aa6537.