PMID- 32708851
OWN - NLM
STAT- PubMed-not-MEDLINE
LR  - 20200827
IS  - 1424-8220 (Electronic)
IS  - 1424-8220 (Linking)
VI  - 20
IP  - 14
DP  - 2020 Jul 17
TI  - EDSSA: An Encoder-Decoder Semantic Segmentation Networks Accelerator on 
      OpenCL-Based FPGA Platform.
LID - 10.3390/s20143969 [doi]
LID - 3969
AB  - Visual semantic segmentation, which is represented by the semantic segmentation 
      network, has been widely used in many fields, such as intelligent robots, 
      security, and autonomous driving. However, these Convolutional Neural Network 
      (CNN)-based networks have high requirements for computing resources and 
      programmability for hardware platforms. For embedded platforms and terminal 
      devices in particular, Graphics Processing Unit (GPU)-based computing platforms 
      cannot meet these requirements in terms of size and power consumption. In 
      contrast, the Field Programmable Gate Array (FPGA)-based hardware system not only 
      has flexible programmability and high embeddability, but can also meet lower 
      power consumption requirements, which make it an appropriate solution for 
      semantic segmentation on terminal devices. In this paper, we demonstrate EDSSA-an 
      Encoder-Decoder semantic segmentation networks accelerator architecture which can 
      be implemented with flexible parameter configurations and hardware resources on 
      the FPGA platforms that support Open Computing Language (OpenCL) development. We 
      introduce the related technologies, architecture design, algorithm optimization, 
      and hardware implementation of the Encoder-Decoder semantic segmentation network 
      SegNet as an example, and undertake a performance evaluation. Using an Intel 
      Arria-10 GX1150 platform for evaluation, our work achieves a throughput higher 
      than 432.8 GOP/s with power consumption of about 20 W, which is a 1.2x times 
      improvement the energy-efficiency ratio compared to a high-performance GPU.
FAU - Huang, Hongzhi
AU  - Huang H
AD  - School of Electronic and Information Engineering, Beijing Jiaotong University, 
      Beijing 100044, China.
FAU - Wu, Yakun
AU  - Wu Y
AD  - School of Electronic and Information Engineering, Beijing Jiaotong University, 
      Beijing 100044, China.
FAU - Yu, Mengqi
AU  - Yu M
AD  - Department of Electronic Engineering and BNRist, Tsinghua University, Beijing 
      100084, China.
FAU - Shi, Xuesong
AU  - Shi X
AUID- ORCID: 0000-0002-3880-4501
AD  - Intel Labs China, Beijing 100090, China.
FAU - Qiao, Fei
AU  - Qiao F
AUID- ORCID: 0000-0002-5054-9590
AD  - Department of Electronic Engineering and BNRist, Tsinghua University, Beijing 
      100084, China.
FAU - Luo, Li
AU  - Luo L
AD  - School of Electronic and Information Engineering, Beijing Jiaotong University, 
      Beijing 100044, China.
FAU - Wei, Qi
AU  - Wei Q
AUID- ORCID: 0000-0003-3189-7562
AD  - Department of Precision Instrument, Tsinghua University, Beijing 100084, China.
FAU - Liu, Xinjun
AU  - Liu X
AD  - Department of Mechanical Engineering, Tsinghua University, Beijing 100084, China.
LA  - eng
PT  - Journal Article
DEP - 20200717
PL  - Switzerland
TA  - Sensors (Basel)
JT  - Sensors (Basel, Switzerland)
JID - 101204366
SB  - IM
PMC - PMC7411893
OTO - NOTNLM
OT  - FPGA
OT  - OpenCL
OT  - framework
OT  - semantic segmentation
COIS- The authors declare no conflict of interest.
EDAT- 2020/07/28 06:00
MHDA- 2020/07/28 06:01
PMCR- 2020/07/01
CRDT- 2020/07/26 06:00
PHST- 2020/05/12 00:00 [received]
PHST- 2020/07/04 00:00 [revised]
PHST- 2020/07/06 00:00 [accepted]
PHST- 2020/07/26 06:00 [entrez]
PHST- 2020/07/28 06:00 [pubmed]
PHST- 2020/07/28 06:01 [medline]
PHST- 2020/07/01 00:00 [pmc-release]
AID - s20143969 [pii]
AID - sensors-20-03969 [pii]
AID - 10.3390/s20143969 [doi]
PST - epublish
SO  - Sensors (Basel). 2020 Jul 17;20(14):3969. doi: 10.3390/s20143969.