PMID- 33551130
OWN - NLM
STAT- PubMed-not-MEDLINE
LR  - 20210920
IS  - 1879-2022 (Electronic)
IS  - 0019-0578 (Linking)
VI  - 117
DP  - 2021 Nov
TI  - Design, FPGA implementation and statistical analysis of a high-speed and low-area 
      TRNG based on an AES s-box post-processing technique.
PG  - 160-171
LID - S0019-0578(21)00064-1 [pii]
LID - 10.1016/j.isatra.2021.01.054 [doi]
AB  - The statistical weakness problem occurring as a result of physical randomness is 
      an important shortcoming of TRNGs. Post-processing techniques are generally used 
      in the literature to overcome this shortcoming. In this study, the hardware 
      implementation of Advanced Encryption Standard (AES) substitution box 
      (s-box)-based novel post-processing technique is presented. The low-cost novel 
      method is based on the substitution s-box transformations and can successfully 
      remove the statistical weakness problem of TRNGs. The real-time verification of 
      the proposed post-processing is done by applying ring oscillator (RO) based TRNG 
      architecture in four different scenarios on Field Programmable Gate Array (FPGA) 
      environment. Successful statistical results obtained from bias, correlation, 
      entropy and NIST 800-22 tests confirm the usability of the proposed method for 
      cryptographic purposes. The low area-energy requirement, practicality and 
      compressionless properties of the post-processing provide better tradeoff for 
      TRNG compared to known methods in the literature. For this reason, TRNG's 
      performance is high. Furthermore, the presented study is important in 
      demonstrating that s-boxes with good mathematical encryption properties can also 
      be used for different cryptographic purposes.
CI  - Copyright (c) 2021 ISA. Published by Elsevier Ltd. All rights reserved.
FAU - Gari Pcan, Ali Murat
AU  - Gari Pcan AM
AD  - Department of Computer Engineering, Firat University, Elazig, Turkey. Electronic 
      address: 161129203@firat.edu.tr.
FAU - Erdem, Ebubekir
AU  - Erdem E
AD  - Department of Computer Engineering, Firat University, Elazig, Turkey. Electronic 
      address: aberdem@firat.edu.tr.
LA  - eng
PT  - Journal Article
DEP - 20210128
PL  - United States
TA  - ISA Trans
JT  - ISA transactions
JID - 0374750
SB  - IM
OTO - NOTNLM
OT  - AES s-box
OT  - Jitter
OT  - Post-processing
OT  - Ring oscillators
OT  - TRNG
COIS- Declaration of Competing Interest The authors declare that they have no known 
      competing financial interests or personal relationships that could have appeared 
      to influence the work reported in this paper.
EDAT- 2021/02/09 06:00
MHDA- 2021/02/09 06:01
CRDT- 2021/02/08 05:29
PHST- 2020/01/09 00:00 [received]
PHST- 2021/01/06 00:00 [revised]
PHST- 2021/01/25 00:00 [accepted]
PHST- 2021/02/09 06:00 [pubmed]
PHST- 2021/02/09 06:01 [medline]
PHST- 2021/02/08 05:29 [entrez]
AID - S0019-0578(21)00064-1 [pii]
AID - 10.1016/j.isatra.2021.01.054 [doi]
PST - ppublish
SO  - ISA Trans. 2021 Nov;117:160-171. doi: 10.1016/j.isatra.2021.01.054. Epub 2021 Jan 
      28.