PMID- 34063441 OWN - NLM STAT- PubMed-not-MEDLINE LR - 20210605 IS - 2072-666X (Print) IS - 2072-666X (Electronic) IS - 2072-666X (Linking) VI - 12 IP - 5 DP - 2021 May 15 TI - High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems. LID - 10.3390/mi12050560 [doi] LID - 560 AB - Dynamic data security in embedded systems is raising more and more concerns in numerous safety-critical applications. In particular, the data exchanges in embedded Systems-on-Chip (SoCs) using main memory are exposing many security vulnerabilities to external attacks, which will cause confidential information leakages and program execution failures for SoCs at key points. Therefore, this paper presents a security SoC architecture with integrating a four-parallel Advanced Encryption Standard-Galois/Counter Mode (AES-GCM) cryptographic accelerator for achieving high-efficiency data processing to guarantee data exchange security between the SoC and main memory against bus monitoring, off-line analysis, and data tampering attacks. The architecture design has been implemented and verified on a Xilinx Virtex-5 Field Programmable Gate Array (FPGA) platform. Based on evaluation of the cryptographic accelerator in terms of performance overhead, security capability, processing efficiency, and resource consumption, experimental results show that the parallel cryptographic accelerator does not incur significant performance overhead on providing confidentiality and integrity protections for exchanged data; its average performance overhead reduces to as low as 2.65% on typical 8-KB I/D-Caches, and its data processing efficiency is around 3 times that of the pipelined AES-GCM construction. The reinforced SoC under the data tampering attacks and benchmark tests confirms the effectiveness against external physical attacks and satisfies a good trade-off between high-efficiency and hardware overhead. FAU - Zhang, Zhun AU - Zhang Z AUID- ORCID: 0000-0001-7726-4547 AD - School of Electronic and Information Engineering, Beihang University, Beijing 100191, China. FAU - Wang, Xiang AU - Wang X AD - School of Electronic and Information Engineering, Beihang University, Beijing 100191, China. FAU - Hao, Qiang AU - Hao Q AD - School of Electronic and Information Engineering, Beihang University, Beijing 100191, China. FAU - Xu, Dongdong AU - Xu D AD - School of Electronic and Information Engineering, Beihang University, Beijing 100191, China. FAU - Zhang, Jinlei AU - Zhang J AD - School of Electronic and Information Engineering, Beihang University, Beijing 100191, China. FAU - Liu, Jiakang AU - Liu J AD - School of Electronic and Information Engineering, Beihang University, Beijing 100191, China. FAU - Ma, Jinhui AU - Ma J AD - School of Electronic and Information Engineering, Beihang University, Beijing 100191, China. LA - eng GR - 60973106 81571142/National Natural Science Foundation of China/ GR - 61232009/Key Project of National Natural Science Foundation of China/ GR - 2011AA010404/National 863 Project of China/ PT - Journal Article DEP - 20210515 PL - Switzerland TA - Micromachines (Basel) JT - Micromachines JID - 101640903 PMC - PMC8155854 OTO - NOTNLM OT - AES-GCM OT - SoC OT - cryptographic accelerator OT - dynamic data security OT - hardware security COIS- The authors declare no conflict of interest. EDAT- 2021/06/03 06:00 MHDA- 2021/06/03 06:01 PMCR- 2021/05/15 CRDT- 2021/06/02 01:06 PHST- 2021/04/13 00:00 [received] PHST- 2021/05/07 00:00 [revised] PHST- 2021/05/11 00:00 [accepted] PHST- 2021/06/02 01:06 [entrez] PHST- 2021/06/03 06:00 [pubmed] PHST- 2021/06/03 06:01 [medline] PHST- 2021/05/15 00:00 [pmc-release] AID - mi12050560 [pii] AID - micromachines-12-00560 [pii] AID - 10.3390/mi12050560 [doi] PST - epublish SO - Micromachines (Basel). 2021 May 15;12(5):560. doi: 10.3390/mi12050560.