PMID- 36296740
OWN - NLM
STAT- PubMed-not-MEDLINE
LR  - 20221030
IS  - 2079-4991 (Print)
IS  - 2079-4991 (Electronic)
IS  - 2079-4991 (Linking)
VI  - 12
IP  - 20
DP  - 2022 Oct 11
TI  - Challenges for Nanoscale CMOS Logic Based on Two-Dimensional Materials.
LID - 10.3390/nano12203548 [doi]
LID - 3548
AB  - For ultra-scaled technology nodes at channel lengths below 12 nm, two-dimensional 
      (2D) materials are a potential replacement for silicon since even atomically thin 
      2D semiconductors can maintain sizable mobilities and provide enhanced gate 
      control in a stacked channel nanosheet transistor geometry. While theoretical 
      projections and available experimental prototypes indicate great potential for 2D 
      field effect transistors (FETs), several major challenges must be solved to 
      realize CMOS logic circuits based on 2D materials at the wafer scale. This review 
      discusses the most critical issues and benchmarks against the targets outlined 
      for the 0.7 nm node in the International Roadmap for Devices and Systems 
      scheduled for 2034. These issues are grouped into four areas; device scaling, the 
      formation of low-resistive contacts to 2D semiconductors, gate stack design, and 
      wafer-scale process integration. Here, we summarize recent developments in these 
      areas and identify the most important future research questions which will have 
      to be solved to allow for industrial adaptation of the 2D technology.
FAU - Knobloch, Theresia
AU  - Knobloch T
AUID- ORCID: 0000-0001-5156-9510
AD  - Institute for Microelectronics, TU Wien, Gusshausstrasse 27-29/E360, 1040 Vienna, 
      Austria.
FAU - Selberherr, Siegfried
AU  - Selberherr S
AUID- ORCID: 0000-0002-5583-6177
AD  - Institute for Microelectronics, TU Wien, Gusshausstrasse 27-29/E360, 1040 Vienna, 
      Austria.
FAU - Grasser, Tibor
AU  - Grasser T
AUID- ORCID: 0000-0001-6536-2238
AD  - Institute for Microelectronics, TU Wien, Gusshausstrasse 27-29/E360, 1040 Vienna, 
      Austria.
LA  - eng
GR  - I5296-N/FWF Austrian Science Fund/
GR  - I4123-N30/FWF Austrian Science Fund/
GR  - I2606-N30/FWF Austrian Science Fund/
PT  - Journal Article
PT  - Review
DEP - 20221011
PL  - Switzerland
TA  - Nanomaterials (Basel)
JT  - Nanomaterials (Basel, Switzerland)
JID - 101610216
PMC - PMC9609734
OTO - NOTNLM
OT  - 2D materials
OT  - CMOS logic
OT  - Schottky barriers
OT  - charge traps
OT  - contact resistances
OT  - field effect transistors
OT  - nanoscale devices
OT  - nanosheet FET
OT  - process integration
OT  - van der Waals interfaces
COIS- The authors declare no conflict of interest.
EDAT- 2022/10/28 06:00
MHDA- 2022/10/28 06:01
PMCR- 2022/10/11
CRDT- 2022/10/27 01:46
PHST- 2022/09/01 00:00 [received]
PHST- 2022/09/30 00:00 [revised]
PHST- 2022/10/03 00:00 [accepted]
PHST- 2022/10/27 01:46 [entrez]
PHST- 2022/10/28 06:00 [pubmed]
PHST- 2022/10/28 06:01 [medline]
PHST- 2022/10/11 00:00 [pmc-release]
AID - nano12203548 [pii]
AID - nanomaterials-12-03548 [pii]
AID - 10.3390/nano12203548 [doi]
PST - epublish
SO  - Nanomaterials (Basel). 2022 Oct 11;12(20):3548. doi: 10.3390/nano12203548.