PMID- 36679615
OWN - NLM
STAT- PubMed-not-MEDLINE
DCOM- 20230124
LR  - 20230202
IS  - 1424-8220 (Electronic)
IS  - 1424-8220 (Linking)
VI  - 23
IP  - 2
DP  - 2023 Jan 10
TI  - Cost-Effective Network Reordering Using FPGA.
LID - 10.3390/s23020819 [doi]
LID - 819
AB  - The advancement of complex Internet of Things (IoT) devices in recent years has 
      deepened their dependency on network connectivity, demanding low latency and high 
      throughput. At the same time, expanding operating conditions for these devices 
      have brought challenges that limit the design constraints and accessibility for 
      future hardware or software upgrades. These limitations can result in data loss 
      because of out-of-order packets if the design specification cannot keep up with 
      network demands. In addition, existing network reordering solutions become less 
      applicable due to the drastic changes in the type of network endpoints, as IoT 
      devices typically have less memory and are likely to be power-constrained. One 
      approach to address this problem is reordering packets using reconfigurable 
      hardware to ease computation in other functions. Field Programmable Gate Array 
      (FPGA) devices are ideal candidates for hardware implementations at the network 
      endpoints due to their high performance and flexibility. Moreover, previous 
      research on packet reordering using FPGAs has serious design flaws that can lead 
      to unnecessary packet dropping due to blocking in memory. This research proposes 
      a scalable hardware-focused method for packet reordering that can overcome the 
      flaws from previous work while maintaining minimal resource usage and low time 
      complexity. The design utilizes a pipelined approach to perform sorting in 
      parallel and completes the operation within two clock cycles. FPGA resources are 
      optimized using a two-layer memory management system that consumes minimal 
      on-chip memory and registers. Furthermore, the design is scalable to support 
      multi-flow applications with shared memories in a single FPGA chip.
FAU - Hoang, Vinh Quoc
AU  - Hoang VQ
AD  - Department of Electrical and Computer Engineering, University of Houston, 
      Houston, TX 77204, USA.
FAU - Chen, Yuhua
AU  - Chen Y
AUID- ORCID: 0000-0003-3218-1304
AD  - Department of Electrical and Computer Engineering, University of Houston, 
      Houston, TX 77204, USA.
LA  - eng
PT  - Journal Article
DEP - 20230110
PL  - Switzerland
TA  - Sensors (Basel)
JT  - Sensors (Basel, Switzerland)
JID - 101204366
SB  - IM
MH  - Cost-Benefit Analysis
MH  - *Software
MH  - *Computers
MH  - Internet
PMC - PMC9865474
OTO - NOTNLM
OT  - FPGA
OT  - IoT
OT  - network
OT  - reordering
COIS- The authors declare no conflict of interest.
EDAT- 2023/01/22 06:00
MHDA- 2023/01/25 06:00
PMCR- 2023/01/10
CRDT- 2023/01/21 01:55
PHST- 2022/11/29 00:00 [received]
PHST- 2023/01/02 00:00 [revised]
PHST- 2023/01/05 00:00 [accepted]
PHST- 2023/01/21 01:55 [entrez]
PHST- 2023/01/22 06:00 [pubmed]
PHST- 2023/01/25 06:00 [medline]
PHST- 2023/01/10 00:00 [pmc-release]
AID - s23020819 [pii]
AID - sensors-23-00819 [pii]
AID - 10.3390/s23020819 [doi]
PST - epublish
SO  - Sensors (Basel). 2023 Jan 10;23(2):819. doi: 10.3390/s23020819.