PMID- 38004932
OWN - NLM
STAT- PubMed-not-MEDLINE
LR  - 20231127
IS  - 2072-666X (Print)
IS  - 2072-666X (Electronic)
IS  - 2072-666X (Linking)
VI  - 14
IP  - 11
DP  - 2023 Nov 8
TI  - An FPGA-Based High-Performance Stateful Packet Processing Method.
LID - 10.3390/mi14112074 [doi]
LID - 2074
AB  - Compared to a stateless data plane, a stateful data plane offloads part of state 
      information and control logic from a controller to a data plane to reduce 
      communication overhead and improve packet processing efficiency. However, 
      existing methods for implementing stateful data planes face challenges, 
      particularly maintaining state consistency during packet processing and improving 
      throughput performance. This paper presents a high-performance, FPGA (Field 
      Programmable Gate Array)-based stateful packet processing approach, which 
      addresses these challenges utilizing the PHV (Packet Header Vector) dynamic 
      scheduling technique to ensure flow state consistency. Our experiments 
      demonstrate that the proposed method could operate at 200 MHz while adding 3-12 
      microseconds latency. The method we proposed also provides a considerable degree 
      of programmability.
FAU - Lu, Rui
AU  - Lu R
AD  - National Network New Media Engineering Research Center, Institute of Acoustics, 
      Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, 
      Beijing 100190, China.
AD  - School of Electronic, Electrical and Communication Engineering, University of 
      Chinese Academy of Sciences, No. 19(A), Yuquan Road, Shijingshan District, 
      Beijing 100049, China.
FAU - Guo, Zhichuan
AU  - Guo Z
AD  - National Network New Media Engineering Research Center, Institute of Acoustics, 
      Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, 
      Beijing 100190, China.
AD  - School of Electronic, Electrical and Communication Engineering, University of 
      Chinese Academy of Sciences, No. 19(A), Yuquan Road, Shijingshan District, 
      Beijing 100049, China.
AD  - Suzhou Haiwang Network Technologies Co., Ltd., Suzhou 215163, China.
LA  - eng
GR  - 424 2022YFB2901004/National Key Research and Development Program of China/
PT  - Journal Article
DEP - 20231108
PL  - Switzerland
TA  - Micromachines (Basel)
JT  - Micromachines
JID - 101640903
PMC - PMC10673001
OTO - NOTNLM
OT  - FPGA
OT  - PHV dynamic scheduling
OT  - configurable
OT  - stateful data plane
COIS- The authors declare no conflict of interest.
EDAT- 2023/11/25 12:45
MHDA- 2023/11/25 12:46
PMCR- 2023/11/08
CRDT- 2023/11/25 01:25
PHST- 2023/09/30 00:00 [received]
PHST- 2023/11/01 00:00 [revised]
PHST- 2023/11/04 00:00 [accepted]
PHST- 2023/11/25 12:46 [medline]
PHST- 2023/11/25 12:45 [pubmed]
PHST- 2023/11/25 01:25 [entrez]
PHST- 2023/11/08 00:00 [pmc-release]
AID - mi14112074 [pii]
AID - micromachines-14-02074 [pii]
AID - 10.3390/mi14112074 [doi]
PST - epublish
SO  - Micromachines (Basel). 2023 Nov 8;14(11):2074. doi: 10.3390/mi14112074.